There are conventionally known switches that connect arithmetic processing unit to memories. An example of this type of switch includes a known switch that connects, in a system in which central processing units (CPUs) that function as arithmetic processing units are connected to memories that function as storage devices, an arbitrary CPU to an arbitrary memory by switching the connection.
In the following, an example of such a switch will be described with reference to FIG. 11. FIG. 11 is a schematic diagram illustrating an example of a switch that connects CPUs to memories. An information processing apparatus 60 illustrated in FIG. 11 includes a plurality of CPUs 61 to 64, a switch 65, and a plurality of memories 66 to 69. Furthermore, the switch 65 is connected to each of the CPUs 61 to 64 and each of the memories 66 to 69.
For example, when the switch 65 receives an instruction from a user to connect the CPU 61 to the memory 66, the switch 65 connects the CPU 61 to the memory 66 and relays data that is sent and received between the CPU 61 and the memory 66. Furthermore, for example, when the switch 65 receives an instruction from a user to connect the CPU 62, the memory 67, and the memory 68, the switch 65 connects the CPU 62 to the memory 67, connects the CPU 62 to the memory 68, and then relays data that is sent and received among the CPU 62, the memory 67, and the memory 68. In this way, by combining the specified arbitrary CPU with the specified arbitrary memory, the switch 65 enhances the flexibility of a system of the information processing apparatus 60. With regard to the conventional techniques, see, for example, Japanese Laid-open Patent Publication No. 2003-337758, Japanese Laid-open Patent Publication No. 2001-318901, and Hideharu Amano “Parallel Computers” Information system schoolbook series 18th volume, Shokodo Co. Ltd., p. 8-9p, Jun. 5, 1996.
However, with the technology in which a single switch connects CPUs to memories, if the switch has failed, a memory access is not possible and the failure affects all of the CPUs. Consequently, there is a problem in that the reliability of the information processing apparatus becomes low.
Thus, in order to improve the reliability, there may be a method of multiplexing a switch that connects CPUs to memories and, if an active system switch has failed, continuing a process by using a standby system switch. However, if the switch that connects the CPUs to the memories is multiplexed, a method of detecting a failure from the active system switch or a method of switching the active system switch at an appropriate timing needs to be implemented.